High-speed synchronous ICs depend on far more than an ideal clock waveform. Physical clock signals travel through buffers, interconnect, gating structures, and large distribution networks before reaching sequential elements. Resistance, capacitance, inductance, loading, process variation, voltage noise, and temperature gradients create arrival-time differences that directly affect setup and hold margins. Clock grids, H-trees, spines, ad hoc trees, and hybrid distribution structures provide different trade-offs among skew, delay, power, routing resources, and implementation complexity. Low-resistance global wiring, repeater placement, shielding, return-current paths, and transmission-line effects become increasingly important as clock frequency and die size increase. Clock skew is treated as a timing-budget problem rather than a single fixed physical quantity. Systematic mismatch, random process variation, environmental drift, and jitter have different behavior and require different mitigation methods. Setup and hold checks may require different skew allowances, while local and global clock domains can use different budgets according to physical distance and distribution structure....