Low-Power Simulation and Verification Methodology

Low-power verification ensures that a digital design behaves correctly when power is selectively removed, restored, or operated under different supply conditions. Traditional functional simulation assumes continuous power availability, but power-managed systems require explicit modeling of state loss, isolation, retention, voltage-domain crossings, and shutdown behavior. These effects must be verified because they can change functional behavior even when the RTL logic is otherwise correct. Power-aware simulation models the physical consequences of power transitions. When a domain is powered off, non-retained state is corrupted to represent real state loss. Isolation logic clamps outputs from inactive domains to safe values so that powered-on logic does not receive unknown or floating signals. Retention logic preserves selected state across shutdown and restores it during power-up. Correct sequencing of isolation, save, power shutoff, power restoration, restore, and isolation release is essential for predictable recovery. Retention behavior depends on the underlying retention architecture. Edge-based and level-based balloon latch schemes use different save and restore semantics, while master–slave latch retention relies on retention conditions and always-alive storage elements. Verification must check control polarity, timing relationships, retention supply availability, reset interaction, and whether the retained state is sufficient for correct restart after power restoration. Power intent provides the formal description that connects functional design with power-aware behavior. IEEE 1801 UPF defines power domains, supply sets, power modes, isolation strategies, retention strategies, level shifters, power switches, and domain interface rules. Accurate UPF specification allows tools to interpret power states consistently and to apply low-power semantics during simulation, static checking, implementation, and equivalence analysis. Low-power verification includes several complementary check categories. Power intent quality checks validate syntax, completeness, and semantic consistency. Structural checks confirm that isolation cells, retention cells, level shifters, and power switches are inserted and connected correctly. Rule checks verify that control conditions, clamp values, domain crossings, and supply relationships match the intended power architecture. Functional checks validate real behavior during power transitions. Power-aware equivalence checking confirms that both logic function and power behavior remain consistent across RTL, gate-level, and implementation netlists. It accounts for inserted low-power cells, domain boundaries, retention behavior, isolation behavior, and shutoff semantics. A complete verification strategy combines simulation, static analysis, structural validation, functional rule checking, and equivalence checking to preserve power intent from specification through implementation. Catalogue: Power as a Primary Design Constraint Low-Power Verification Complexity Fundamental Terms of Low-Power Simulation State Loss in Low-Power Simulation Example: State Loss in Low-Power Simulation (I) Example: State Loss in Low-Power Simulation (II) Port Isolation in Low-Power Simulation Example: Port Isolation in Low-Power Simulation State Retention in Low-Power Simulation Fundamentals of Low-Power Simulation Edge-Based Balloon Latch Power Cycle Level-Based Balloon Latch Power Cycle Master–Slave Latch Power Cycle Power Intent Definition and Standardization Power Domain Concepts and Classification Power Modes Definition and Usage Overview of Low-Power Design Techniques Architecture of a Low-Power System Low-Power Verification Scope Power Intent Quality Checks Structural Checks Rule Checks Power Domain Equivalence Checks Isolation Function Checks Retention Function Checks Shutoff Function Checks Low Power Verification Checks Low Power Equivalence Checks