Low-Power Simulation and Verification Methodology
Verify low-power digital designs using power-aware simulation, UPF intent checks, structural validation, isolation and retention checks, shutoff verification, and power-aware equivalence to ensure correct behavior across power modes and transitions.
Verify low-power digital designs using power-aware simulation, UPF intent checks, structural validation, isolation and retention checks, shutoff verification, and power-aware equivalence to ensure correct behavior across power modes and transitions.
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Description
Low-power verification ensures that a digital design behaves correctly when power is selectively removed, restored, or operated under different supply conditions. Traditional functional simulation assumes continuous power availability, but power-managed systems require explicit modeling of state loss, isolation, retention, voltage-domain crossings, and shutdown behavior. These effects must be verified because they can change functional behavior even when the RTL logic is otherwise correct. Power-aware simulation models the physical consequences of power transitions. When a domain is powered off, non-retained state is corrupted to represent real state loss. Isolation logic clamps outputs from inactive domains to safe values so that powered-on logic does not receive unknown or floating signals. Retention logic preserves selected state across shutdown and restores it during power-up. Correct sequencing of isolation, save, power shutoff, power restoration, restore, and isolation release is essential for predictable recovery. Retention behavior depends on the underlying retention architecture. Edge-based and level-based balloon latch schemes use different save and restore semantics, w...
This resource includes
Description
Low-power verification ensures that a digital design behaves correctly when power is selectively removed, restored, or operated under different supply conditions. Traditional functional simulation assumes continuous power availability, but power-managed systems require explicit modeling of state loss, isolation, retention, voltage-domain crossings, and shutdown behavior. These effects must be verified because they can change functional behavior even when the RTL logic is otherwise correct. Power-aware simulation models the physical consequences of power transitions. When a domain is powered off, non-retained state is corrupted to represent real state loss. Isolation logic clamps outputs from inactive domains to safe values so that powered-on logic does not receive unknown or floating signals. Retention logic preserves selected state across shutdown and restores it during power-up. Correct sequencing of isolation, save, power shutoff, power restoration, restore, and isolation release is essential for predictable recovery. Retention behavior depends on the underlying retention architecture. Edge-based and level-based balloon latch schemes use different save and restore semantics, w...
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