Description

Formal verification technology has a wide range of applications and places high demands on engineers, especially in formal signoff delivery, where the work of formal verification engineers is quite different from that of traditional simulation verification engineers. For traditional simulation verification engineers, their main task is to write test cases to verify the functional correctness of designs. However, for formal verification engineers, their primary work is to model design behavior, which requires a thorough and comprehensive understanding of design functions. Formal verification engineers need to have systematic logical thinking and be able to extract functional features from design specifications to build accurate formal models. This requires not only a solid design foundation but also proficiency in formal verification tools and algorithms to abstract verification problems into mathematical models and complete functional verification of designs. This course serves as a fundamental introductory course, covering all important technical points in the current field of formal verification. For each technical point, the course mainly provides conceptual introductions,...