Formal verification applies logic-based techniques to verify that a hardware design meets its specification across all possible input combinations and states. It uses a property-centric approach, driven by assertions and assumptions that define expected design behavior and environmental constraints. Assertions capture critical safety and liveness conditions that must always or eventually hold. Assumptions constrain the state space to valid input scenarios, preventing unrealistic or undefined states from entering analysis. A complete and well-structured formal model ensures rigorous, automated analysis of functional correctness. A central technical aspect of formal verification is the exploration of the design’s state space. This space grows exponentially with design complexity, making performance a key concern. Formal tools rely on symbolic reasoning to navigate this space efficiently. Concepts like the Cone of Influence help reduce proof complexity by focusing the engine on relevant logic elements only. Additional techniques such as design abstraction, property decomposition, and compositional reasoning help improve convergence and reduce proof runtime. Proper formal setup requir...