Microarchitecture defines how an instruction-set architecture is realized using registers, ALUs, memories, multiplexers, datapaths, and control logic. Architectural state and instruction behavior are translated into synchronized data movement and state transitions. Datapath construction, instruction decoding, immediate handling, memory access, register writeback, program-counter updates, and conditional execution establish the fundamental structure required to implement ARM-style processor behavior. Single-cycle, multicycle, and pipelined organizations expose different performance and hardware trade-offs. A single-cycle processor completes every instruction in one long cycle and provides simple control with CPI equal to one. A multicycle processor divides execution into shorter steps, reuses memory and ALU resources, and stores intermediate values in nonarchitectural registers under finite-state control. A five-stage pipeline overlaps Fetch, Decode, Execute, Memory, and Writeback to improve instruction throughput, while pipeline registers and the slowest stage determine achievable clock frequency. Concurrent instruction execution introduces RAW dependencies, load-use stalls, bran...