Real Number Modeling for Mixed-Signal Verification

Real Number Modeling provides a practical way to represent analog and mixed-signal behavior inside digital-centric verification environments. Instead of solving every transistor, node voltage, and branch current through a continuous analog solver, RNM describes analog behavior as real-valued signal flow. Values are represented with floating-point real numbers, while time advances through discrete events, sampled updates, clocked behavior, or scheduled computation. This approach is especially useful for mixed-signal SoCs where full-chip verification requires speed, repeatability, and broad scenario coverage. Mixed-signal verification faces a persistent performance gap between analog and digital simulation. Digital verification scales through automation, metric-driven methods, reusable testbenches, coverage collection, and nightly regression. Analog simulation remains limited by detailed electrical solving, convergence behavior, and runtime cost. RNM helps move selected analog behavior from the sparse-matrix solver into the event-driven solver, allowing analog-related functionality to participate in fast full-chip verification without requiring transistor-level simulation for every run. RNM supports DMS flows where analog and mixed-signal blocks are replaced by real-number behavioral models. These models can be validated against transistor-level or analog behavioral references, then reused in digital SoC verification. This enables practical checks for block connectivity, power-domain connections, dangling nodes, control interaction, and system-level mixed-signal behavior. For BigD/smallA designs, RNM provides a strong balance between simulation performance and functional confidence. The modeling decision depends on abstraction level, return on investment, language capability, and verification intent. High-frequency blocks, long-running analog behavior, converters, and blocks that consume large simulation time are strong candidates. Details that do not affect functional testing can often be simplified or omitted. Verilog-AMS wreal, SystemVerilog RNM, VHDL real, Verilog real, and e language support provide different levels of real-valued modeling capability, including ports, nettypes, resolution behavior, multiple contributors, and testbench access. RNM does not remove the need for transistor-level or AMS simulation when detailed electrical accuracy is required. Its value is strongest when analog behavior can be expressed as signal flow and verified through digital-speed execution. Used carefully, RNM improves predictability, productivity, and quality by making mixed-signal behavior available to scalable digital verification methods while preserving the analog functionality needed for full-chip validation. Catalogue: RNM and Mixed-Signal Terms Mixed-Signal Verification Challenge Widening Performance Gap Analog Precision with RNM DMS and AMS Simulation Mixed-Signal Modeling Formats Why Real Number Modeling Analog vs. Real Modeling Analog vs. Discrete Real Models Accuracy and Performance Tradeoff Effort and Performance Tradeoff RNM for DMS Verification Real Number Modeling Basics RNM Limitation Boundaries RNM Language Approaches (I) RNM Language Approaches (II) RNM Model Ownership Choosing Analog Blocks for RNM Model Only What Matters RNM Simulation Speedup