UVM-MS Architecture for Mixed-Signal Verification
UVM-MS extends UVM for mixed-signal verification by connecting UVCs to analog resources through MS Bridges, proxy APIs, and SV interfaces, enabling controlled analog stimulus, model abstraction, coverage collection, and self-checking across AMS and DMS environments.
UVM-MS extends UVM for mixed-signal verification by connecting UVCs to analog resources through MS Bridges, proxy APIs, and SV interfaces, enabling controlled analog stimulus, model abstraction, coverage collection, and self-checking across AMS and DMS environments.
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Description
UVM-MS provides a structured way to apply UVM-style verification to analog and mixed-signal behavior. Standard UVM is effective for transaction-based digital verification, but mixed-signal DUTs require a mechanism for driving and observing continuous electrical signals. UVM-MS addresses this gap through a Mixed-Signal Bridge placed between UVCs and the MS-DUT. The bridge allows sequence-driven control parameters to reach analog resources that can generate, condition, and observe signals at DUT pins. The architecture centers on three cooperating elements: the SV interface, the mixed-signal proxy, and the analog resource. The SV interface supports reusable logic, real, nettype, and RNM-style communication. The proxy API passes analog attributes that are not well suited to ordinary SV interface connections. The analog resource converts those attributes into signal behavior, such as ramping supplies, sine waves, sawtooth waveforms, noise injection, drive-strength effects, loading, impedance, and voltage or current conditioning. Analog resources can be implemented with SV, Verilog, Verilog-AMS, SV-RNM, or SPICE-derived structures. Their abstraction level can match the abstraction of t...
This resource includes
Description
UVM-MS provides a structured way to apply UVM-style verification to analog and mixed-signal behavior. Standard UVM is effective for transaction-based digital verification, but mixed-signal DUTs require a mechanism for driving and observing continuous electrical signals. UVM-MS addresses this gap through a Mixed-Signal Bridge placed between UVCs and the MS-DUT. The bridge allows sequence-driven control parameters to reach analog resources that can generate, condition, and observe signals at DUT pins. The architecture centers on three cooperating elements: the SV interface, the mixed-signal proxy, and the analog resource. The SV interface supports reusable logic, real, nettype, and RNM-style communication. The proxy API passes analog attributes that are not well suited to ordinary SV interface connections. The analog resource converts those attributes into signal behavior, such as ramping supplies, sine waves, sawtooth waveforms, noise injection, drive-strength effects, loading, impedance, and voltage or current conditioning. Analog resources can be implemented with SV, Verilog, Verilog-AMS, SV-RNM, or SPICE-derived structures. Their abstraction level can match the abstraction of t...
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