UVM-MS Architecture for Mixed-Signal Verification

UVM-MS provides a structured way to apply UVM-style verification to analog and mixed-signal behavior. Standard UVM is effective for transaction-based digital verification, but mixed-signal DUTs require a mechanism for driving and observing continuous electrical signals. UVM-MS addresses this gap through a Mixed-Signal Bridge placed between UVCs and the MS-DUT. The bridge allows sequence-driven control parameters to reach analog resources that can generate, condition, and observe signals at DUT pins. The architecture centers on three cooperating elements: the SV interface, the mixed-signal proxy, and the analog resource. The SV interface supports reusable logic, real, nettype, and RNM-style communication. The proxy API passes analog attributes that are not well suited to ordinary SV interface connections. The analog resource converts those attributes into signal behavior, such as ramping supplies, sine waves, sawtooth waveforms, noise injection, drive-strength effects, loading, impedance, and voltage or current conditioning. Analog resources can be implemented with SV, Verilog, Verilog-AMS, SV-RNM, or SPICE-derived structures. Their abstraction level can match the abstraction of the MS-DUT, allowing the same verification structure to move between faster model-based verification and more detailed mixed-signal behavior. This supports top-down verification, early integration, and parallel development while preserving the role of detailed analog verification for performance-focused checks such as power, frequency response, transient behavior, noise, and electrical accuracy. The proxy structure solves several practical limitations of SV interfaces in mixed-signal verification. It avoids datatype ripple through UVM configuration, supports class-based API extension, and provides a cleaner path for analog attributes to reach bridge-local resources. Push, pull, push-sync, and monitored real-value mechanisms support control, synchronization, measurement, checking, and coverage collection. This makes analog behavior accessible to UVM-style monitors, scoreboards, and self-checking environments. SystemVerilog interfaces remain important for reusable digital communication. Existing SV interfaces can be preserved for logic-style connectivity, reducing rework from existing verification collateral. Interface concepts such as named signal bundles, directionless interface ports, parent-level instantiation, and centralized bus declaration simplify design connectivity and improve maintainability. In UVM-MS, these interface mechanisms work together with proxy APIs and analog resources to form a practical verification structure for AMS and DMS designs. Catalogue: Mixed-Signal Verification Challenges Top-Down MS Verification Flow Model-Based MS Verification UVM Overview UVM Verification Library Why UVM-MS Matters UVM-MS Testbench Requirements Driving Analog Signals from UVM Multi-Generator Waveform Control UVM-MS Architecture Bridge Inside the MS Bridge Analog Resource for UVM-MS Analog Resource Connectivity MS Bridge and OOMR Mixed-Signal Proxy Purpose Implementing the MS Proxy MS Proxy API Functions SystemVerilog Interface Basics SystemVerilog Interface Concept Interface Connection Example SV Interface in UVM-MS