Low-power IC design requires more than selecting individual power-saving techniques. Power targets must be translated into a repeatable engineering methodology that connects modeling, analysis, implementation, optimization, and verification across system-level design, RTL, synthesis, physical implementation, and sign-off. Power models and current-waveform models establish the foundation for accurate estimation, while continuous power regression provides visibility into changing power behavior across operating modes and development milestones. System-level power reduction focuses on controlling effective switching activity and supply voltage through operating modes, voltage and frequency control, parallelism, pipelining, and memory organization. RTL techniques such as clock gating, glitch-free gated-clock structures, data gating, and operand isolation suppress unnecessary switching before physical implementation. Memory banking and access reduction lower both access frequency and the energy required by individual memory operations. Each technique must be evaluated against timing, area, implementation complexity, and actual workload behavior rather than applied indiscriminately. Ph...