DFT-Based IC Testing Fundamentals

Integrated circuits are manufactured through highly complex processes where tiny variations can introduce defects that are invisible at the design level. These defects may cause incorrect logic values, timing failures, or unstable behavior that only appears under certain conditions. Detecting such problems requires systematic methods that go far beyond simply checking whether a circuit appears to function correctly. Testing exists to expose hidden failures, control internal states, and observe circuit responses in a predictable and repeatable way. Testing relies on the ability to drive signals into a circuit and observe how the circuit reacts. When control or observation is limited, faults can remain hidden even when they exist in silicon. Physical defects are therefore represented using abstract fault models that describe how a circuit behaves when something is wrong. Static faults capture permanent logic failures, while dynamic faults represent timing-related behavior such as slow signal transitions caused by resistive defects. These abstractions make it possible to reason about failures without directly seeing the physical defect. As designs grow larger and include memory and feedback, testing becomes increasingly difficult. Sequential logic stores state, making fault effects dependent on history rather than a single input pattern. To address this, scan-based structures are used to transform sequential elements into controllable and observable points. By shifting data in and out of scan chains, internal states can be set and observed directly, allowing systematic fault detection even in complex designs. Automatic test pattern generation applies formal logic techniques to create patterns that activate faults and propagate their effects to observable outputs. Fault sensitization ensures that a defect influences circuit behavior, while propagation carries that influence through logic paths to a point that can be measured. Justification ensures that all required signal values are consistent. These steps form a structured process that replaces manual reasoning with algorithmic generation of effective tests. Manufacturing environments impose strict limits on test time and data volume. Excessive test patterns increase cost and reduce throughput. Techniques such as test compaction reduce redundant patterns while preserving fault coverage. Built-in self-test moves part of the testing logic into the chip itself, reducing reliance on external equipment. Scan compression further lowers data volume and test time, enabling large designs to be tested efficiently. Even with advanced methods, some defects escape detection. Escaped defects reduce fault coverage and can cause failures at the system level. Understanding why escapes occur and how they affect products is critical for improving test quality. Diagnostic techniques analyze failing responses, trace fault effects backward through logic, and correlate miscompares with likely defect locations. These methods support yield improvement, quality control, and long-term process learning.