MemberDFT-Based IC Testing Fundamentals
How Integrated Circuits Are Tested After Manufacturing Using DFT Techniques
This course introduces the fundamental concepts of integrated circuit manufacturing test. It explains how defects are modeled as faults, how scan and ATPG enable systematic testing, and how optimization and diagnostics support product quality and reliable production.
This course introduces the fundamental concepts of integrated circuit manufacturing test. It explains how defects are modeled as faults, how scan and ATPG enable systematic testing, and how optimization and diagnostics support product quality and reliable production.
This course includes
What you'll learn
Who is this course for
Requirements
Description
Integrated circuits are manufactured through highly complex processes where tiny variations can introduce defects that are invisible at the design level. These defects may cause incorrect logic values, timing failures, or unstable behavior that only appears under certain conditions. Detecting such problems requires systematic methods that go far beyond simply checking whether a circuit appears to function correctly. Testing exists to expose hidden failures, control internal states, and observe circuit responses in a predictable and repeatable way. Testing relies on the ability to drive signals into a circuit and observe how the circuit reacts. When control or observation is limited, faults can remain hidden even when they exist in silicon. Physical defects are therefore represented using abstract fault models that describe how a circuit behaves when something is wrong. Static faults capture permanent logic failures, while dynamic faults represent timing-related behavior such as slow signal transitions caused by resistive defects. These abstractions make it possible to reason about failures without directly seeing the physical defect. As designs grow larger and include memory and ...
This course includes
What you'll learn
Who is this course for
Requirements
Description
Integrated circuits are manufactured through highly complex processes where tiny variations can introduce defects that are invisible at the design level. These defects may cause incorrect logic values, timing failures, or unstable behavior that only appears under certain conditions. Detecting such problems requires systematic methods that go far beyond simply checking whether a circuit appears to function correctly. Testing exists to expose hidden failures, control internal states, and observe circuit responses in a predictable and repeatable way. Testing relies on the ability to drive signals into a circuit and observe how the circuit reacts. When control or observation is limited, faults can remain hidden even when they exist in silicon. Physical defects are therefore represented using abstract fault models that describe how a circuit behaves when something is wrong. Static faults capture permanent logic failures, while dynamic faults represent timing-related behavior such as slow signal transitions caused by resistive defects. These abstractions make it possible to reason about failures without directly seeing the physical defect. As designs grow larger and include memory and ...
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EDA Academy is a practical learning platform for engineers in the VLSI and semiconductor industry. We offer structured courses, technical resources, and career-focused training across all major areas of chip design and verification — from Verilog to Physical Design, from fundamentals to advanced topics. Learn at your own pace, explore member-exclusive content, or join as an instructor to share your expertise. Lear...
