CMOS VLSI design connects MOS devices, static and sequential logic, layout, fabrication, processor architecture, HDL, circuit optimization, floorplanning, verification, tapeout, packaging, and testing to explain how digital functions become reliable, power-aware, manufacturable silicon systems.
Created by Peter Yo
Last update 09/2026
Level Beginner
Language English
5.0
(0)
0
students
CMOS Chip Design from Logic to Manufacturing
CMOS VLSI design connects MOS devices, static and sequential logic, layout, fabrication, processor architecture, HDL, circuit optimization, floorplanning, verification, tapeout, packaging, and testing to explain how digital functions become reliable, power-aware, manufacturable silicon systems.
Created by Peter Yo
Last update 09/2026
Level Beginner
Language English
5.0
(0)
0
students
This offering includes
1 module
9 lectures
Access on mobile and computer
3.36 hours on-demand video
Description
CMOS digital design begins with the electrical behavior of nMOS and pMOS transistors and develops into static CMOS logic through complementary pull-up and pull-down networks. Inverters, NAND and NOR gates, compound gates, pass transistors, transmission gates, tristate structures, multiplexers, latches, and flip-flops establish the connection between Boolean functions and transistor-level implementation. Signal restoration, high-impedance states, contention, clocking, state retention, and edge-triggered storage provide the circuit foundation required for larger synchronous systems.
Physical implementation translates these circuits into silicon geometry. CMOS cross-sections, wells, source and drain diffusion, gate structures, contacts, metal layers, photolithography, scalable design rules, standard-cell layouts, stick diagrams, pitch matching, wordslices, bitslices, and slice plans explain how transistor networks become manufacturable layouts. Floorplanning, routing tracks, power rails, array structures, PLA implementation, memory periphery, metal-layer orientation, and routed-density estimation connect logical organization with silicon area, wire length, congestion, performance, an...
This offering includes
1 module
9 lectures
Access on mobile and computer
3.36 hours on-demand video
Description
CMOS digital design begins with the electrical behavior of nMOS and pMOS transistors and develops into static CMOS logic through complementary pull-up and pull-down networks. Inverters, NAND and NOR gates, compound gates, pass transistors, transmission gates, tristate structures, multiplexers, latches, and flip-flops establish the connection between Boolean functions and transistor-level implementation. Signal restoration, high-impedance states, contention, clocking, state retention, and edge-triggered storage provide the circuit foundation required for larger synchronous systems.
Physical implementation translates these circuits into silicon geometry. CMOS cross-sections, wells, source and drain diffusion, gate structures, contacts, metal layers, photolithography, scalable design rules, standard-cell layouts, stick diagrams, pitch matching, wordslices, bitslices, and slice plans explain how transistor networks become manufacturable layouts. Floorplanning, routing tracks, power rails, array structures, PLA implementation, memory periphery, metal-layer orientation, and routed-density estimation connect logical organization with silicon area, wire length, congestion, performance, an...
Seasoned Chip Backend Design Engineer with over 20 years of experience in the integrated circuit design industry. Expertise in physical design, timing closure, and power optimization. Proven track record of delivering high-quality, efficient chip designs while working with leading technology companies.
