Power has become a first-order design constraint in modern CMOS systems. Dynamic power arises mainly from charging and discharging circuit capacitances and is governed by supply voltage, operating frequency, effective capacitance, and switching activity. Short-circuit current adds another dynamic component when pull-up and pull-down networks conduct simultaneously during transitions. Static power remains even without useful switching and includes subthreshold leakage, gate leakage, junction leakage, and contention current. Technology scaling has increased the importance of leakage to the point where both active and idle power require careful control. Dynamic-power reduction depends on lowering unnecessary switching and reducing the energy required for each remaining transition. Clock gating suppresses activity in idle blocks, while careful floorplanning, placement, gate sizing, and interconnect design reduce switched capacitance. Voltage scaling provides especially strong savings because switching power varies approximately with the square of supply voltage. Frequency scaling reduces switching rate and can create timing margin for additional voltage or transistor-size reduction. M...