Digital circuit performance is strongly controlled by the time required for signals to propagate through transistors, logic gates, interconnect, and multistage paths. Delay originates from the charging and discharging of capacitance through finite transistor current. MOS devices exhibit nonlinear electrical behavior, but effective resistance and capacitance provide practical abstractions for understanding digital switching speed. RC representations expose the direct relationship among transistor strength, capacitive loading, signal transition time, and propagation delay. Gate and diffusion capacitance, transistor width, channel length, device mobility, layout geometry, diffusion sharing, and transistor folding all influence effective delay. First-order RC transient response provides a basic timing approximation, while Elmore delay extends this reasoning to RC trees and internal nodes. Parasitic delay represents the intrinsic cost of charging internal capacitance, while effort delay captures the additional cost of external loading. Fanout and electrical effort quantify load, and logical effort measures how efficiently different gate topologies provide output drive relative to an in...