Leakage power is a critical constraint in scaled CMOS design. It comes from current paths that remain active even when logic is not switching, including subthreshold leakage, gate tunneling leakage, and junction leakage. As threshold voltages decrease and gate oxides become thinner, static power can represent a large portion of total chip power, especially in standby modes and large SoCs with many inactive blocks. CMOS leakage control starts with device-level understanding. Multi-Vt optimization balances speed and static power by using Low-Vt cells on timing-critical paths and High-Vt cells in non-critical logic. This technique provides fine-grained leakage reduction without changing functional behavior. Substrate biasing adds another control mechanism by adjusting effective threshold voltage, reducing leakage during low-activity modes and supporting performance recovery when needed. Power shutoff provides stronger leakage reduction by disconnecting inactive logic from its supply. Power switches create virtual power rails and allow selected domains to be turned off when idle. Shutoff granularity affects area, routing, wake-up latency, IR drop, and control complexity. Fine-grained...