Modern CMOS power dissipation is determined by several mechanisms that behave very differently with voltage, frequency, activity, device size, and operating state. Capacitive charging and discharging form the foundation of dynamic power, with switching energy strongly dependent on supply voltage. Signal activity determines how frequently that energy is consumed, making probability propagation, transition statistics, logic topology, reconvergent fan-out, and temporal correlation important for realistic power estimation. Unequal propagation delays introduce glitches and dynamic hazards, adding switching activity that does not contribute to the final logical result. Short-circuit current adds another frequency-dependent power component when PMOS and NMOS devices conduct simultaneously during finite input transitions. Input and output slew rates determine the magnitude of this current, and matching transition times provides a practical way to control the loss. Equivalent-capacitance models allow short-circuit power to be incorporated directly into timing and power analysis. Dynamic dissipation therefore depends on much more than clock frequency: circuit timing, logic structure, data s...