UVM organizes SystemVerilog verification around a persistent component hierarchy and a transaction-oriented object model. uvm_component provides the structural foundation for tests, environments, agents, drivers, monitors, sequencers, and analysis components. Factory registration and standardized construction enable compatible implementations to be replaced through type or instance overrides without changing the surrounding hierarchy. UVM phasing coordinates testbench construction, connection, timed execution, and result processing through build, run-time, and clean-up phases. run_test() establishes the root test and starts this controlled execution flow. Drivers and monitors form the protocol-facing transaction layer. Drivers receive sequence_item objects from sequencers and translate abstract transactions into DUT signal activity through BFMs and virtual interfaces. Monitors remain passive, recognize protocol behavior from DUT signals, reconstruct transaction objects, and broadcast them through analysis ports. Copy-on-write handling protects monitored transactions from later object modification. Agents package sequencers, driver and monitor proxies, BFMs, analysis interfaces, an...